Продажа лидов - Технические переводы

Здравствуйте. Мы постоянно переводим руководства, инструкции и каталоги. Не нравится обычно качество технического перевода. В некоторых вопросах не справляется и крупные компании, а у мелких работа без НДС тоже напрягает. Если вы хотите попробовать, вот небольшой текст для проверки уровня: The module features a front panel Clock Input and a PLL for clock synthesis from internal/external references. The data stream is continuously written in a circular memory buffer. When the trigger occurs, the FPGA writes further N samples for the post trigger and freezes the buffer that can be read by USB or Optical Link. The acquisition can continue without dead time in a new buffer. Each channel has a SRAM Multi-Event Buffer of 192 kS divisible into 1 ÷ 1024 buffers of programmable size. The readout (by USB or Optical Link) of a frozen buffer is independent from the write operations in the active circular buffer (ADC data storage). N6740D supports multi-board synchronization allowing all ADCs to be synchronized to a common clock source and ensuring Trigger time stamps alignment. Once synchronized, all data will be aligned and coherent across multiple N6740 boards. The trigger signal can be provided externally via the front panel Trigger Input as well as via the software, but it can also be generated internally thanks to threshold self-trigger capability.